This invention generally relates to voltage regulation. More particularly, this invention relates to a low-frequency, low-power switching voltage pre-regulator having automatic sleep-mode switchover.
Linear voltage regulators generate a substantially constant output voltage VOUT from a relatively variable input voltage. Linear voltage regulators also provide low quiescent sleep current. Linear voltage regulators are operative to provide the regulated output voltage VOUT over a range of input voltages. Such linear regulators are used to provide dc voltage signals for circuits designed to receive substantially constant voltage levels with low voltage ripple. Linear voltage regulators may also be designed to provide the constant output voltage VOUT independent of a relatively large input voltage VIN. Accordingly, linear voltage regulators that are designed to operate with higher VOUT/VIN ratios are desirable. For example, linear regulators may provide a substantially constant 7.6 Volts output voltage independent of input voltages for input voltage up to a maximum of 42 Volts. Such linear regulators are desirable in devices or electronic circuits having a Voltage source with a variable output that may be configured to provide Voltage signals to other circuitry requiring stable Voltage signals. By way of example, such linear voltage regulators having substantially constant output voltage VOUT and having a large VOUT/VIN ration are desirable in hybrid analog and digital electronic circuits. Such prior art linear regulators, however, typically generate a relatively large amount of heat that is dissipated, for example, through a relatively large metal heat sink mechanically coupled with the linear regulator.
FIG. 1 is a diagram showing a prior art a cascade design voltage regulator 100 having a switching pre-regulator circuit 102 and a linear regulator circuit 104. The switching pre-regulator circuit 102 receives the input voltage VIN at an input terminal 108 and produces a chopped voltage VCH at a junction terminal 110. The chopped voltage VCH is generated by the switching pre-regulator circuit 102 typically through electrical elements such as chokes, and diodes. The magnitude of the chopped voltage VCH is less than the input voltage VIN and substantially within a desired input voltage range for the linear regulator circuit 104. The magnitude of chopped voltage VCH will generally cycle up and down between an upper limit and a lower limit for the switching pre-regulator circuit 102. The cycle is commonly referred to as a limit cycle.
The linear regulator circuit 104 receives the chopped voltage VCH at the junction terminal 110 and generates a smooth, regulated output voltage VOUT of a substantially constant level at its output terminal 112. Because the chopped voltage VCH received by the linear regulator circuit 104 is substantially lower than the input voltage VIN, the linear regulator circuit 104 operates more efficiently dissipating less power and thereby the cascade design voltage regulator 100, has improved voltage conversion efficiency. A cascade design voltage regulator 100 may include a feedback voltage VFB, which is derived from the output voltage VOUT of the linear regulator circuit 104 and received by the switching pre-regulator circuit 102. The switching pre-regulator circuit 102 thereby generates the chopped voltage VCH in response to the feedback voltage VFB.
It is desirable to conserve the amount of power consumed while controlling the operation of the linear voltage regulator circuit 104. Prior art voltage regulators do not provide for control to switch the pre-regulator circuit 102 to a sleep mode when the output voltage VOUT is not needed, or power from the voltage regulator is not needed. For example, the voltage regulator can be placed in a standby condition when a circuit to which the voltage regulator 100 provides the output Voltage VOUT needs minimal power, and thereby minimize the power dissipated by the regulator. It is further desirable that such regulators would be controlled by signals commonly generated by microprocessors. Accordingly, there is a need in the art voltage regulators having a low frequency, low-power switching voltage pre-regulator circuit.
Embodiments of this invention provide low-frequency, low power switching voltage pre-regulator circuit for providing a chopped voltage to a linear voltage regulator circuit.
In view of the above noted limitations of the prior art, an object of the present invention is to provide an improved voltage regulator that minimizes the amount of power dissipated by the voltage regulator circuit and is capable of being controlled with a pulse width modulated (xe2x80x9cPWMxe2x80x9d) signal of the type generally provided by a microprocessors in order to obtain. More particularly, an input is provided to control a voltage pre-regulator circuit to provide a sleep mode for the voltage regulator when a circuit with which the voltage regulator may be coupled does requires minimal power.
In one aspect, a low-frequency switching voltage pre-regulator circuit, includes an input node, a pulse width modulated (xe2x80x9cPWMxe2x80x9d) signal input node; and a chopped voltage node. The input node may be configured to receive an input voltage signal VIN having a magnitude in the range from and including about 20 Volts to and including about 58 Volts. The PWM input node may be configured to receive a PWM signal having a frequency substantially in the range from about 5 kiloHertz to and about 15 kiloHertz and a duty cycle in the range from about 25% to 50%. The pre-regulator circuit may be configured to generate a chopped voltage VCH at the chopped voltage node in response to the PWM signal and the input voltage VIN and independent of the magnitude of the input voltage VIN. The chopped voltage VCH may have a magnitude in the range from about 6 Volts to about 10 Volts.
The low-frequency switching voltage pre-regulator may further include a chopping circuit coupled with the input node, a bucking circuit, a feedback and sense circuit, and a pre-driver switching circuit. The chopping circuit may be configured to receive the input voltage VIN and generates a bucking signal in response to a switching signal. The bucking circuit is coupled with the chopping circuit generates the chopped voltage VCH at a chopped voltage node in response to the bucking signal. The feedback and sense circuit is coupled with the chopped voltage node and provides a feedback signal in response to the magnitude of the chopped voltage VCH. The pre-driver switching circuit is coupled with the PWM input node and with the feedback and sense circuit selectively generates the switching signal in response to the feedback signal and PWM signal.
In a method for controlling a voltage output in response to a input voltage includes selectively generating a chopped voltage signal in response to a pulse width modulated (xe2x80x9cPWMxe2x80x9d) signal received from microprocessor and an input voltage having a magnitude substantially within a range from and including about 20 Volts to and including about 58 Volts, the chopped voltage having a magnitude independent of the input voltage and being substantially within the range from and including about 6 Volts to and including about 10 Volts, the magnitude of the chopped voltage being independent of the magnitude of the input voltage.
The method may further include generating the PWM signal from a microprocessor circuit, wherein the PWM signal has a frequency between about 5 kiloHertz and 15 kiloHertz and about a 33 percent duty cycle.